 |
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
| Datasheet File OCR Text: |
| ltm9005 1 9005p typical a pplica t ion fea t ures a pplica t ions descrip t ion if sampling receiver subsystem the ltm ? 9005 is an if sampling receiver subsystem for wireless base stations and communications test equip- ment. utilizing an integrated system in a package (sip) technology, it includes a downconverting mixer, 140mhz saw filter, two gain stages, a variable attenuator and analog-to-digital converter (adc). the system is tuned for an intermediate frequency (if) of 140mhz and a signal bandwidth of up to 60mhz; contact linear technology regarding customization. the high integration and small package allow for a very compact receiver. the high signal level downconverting mixer is optimized for high linearity, wide dynamic range if sampling ap - plications. it includes a high speed differential lo buffer amplifier driving a double-balanced mixer. broadband, integrated transformers on the rf and lo inputs provide single ended 50 interfaces. the rf and lo inputs are internally matched to 50 from 1.6ghz to 2.3ghz. versions are available with adcs up to 14-bit resolution and 125msps. a separate output supply allows the parallel output bus to drive 0.5v to 3.6v logic. a single-ended clk input controls converter operation. an optional clock duty cycle stabilizer allows high performance at full speed for a wide range of clock duty cycles. simplified if-sampling receiver n fully integrated rf-to-bits if-sampling receiver subsystem n wide rf frequency range: 400mhz to 3.8ghz n 140mhz center frequency internal saw filter n low power adc with up to 14-bit resolution, 125msps sample rate n 16db cascaded nf, 17.7dbm t wo-tone iip3 n 1.2w total power consumption n 50 single-ended rf and lo ports n continuous 20db attenuation range n internal bypass capacitance, no external components required n adc clock duty cycle stabilizer n digital output supply range: 0.5v to 3.6v n 15mm 22mm lga package n base station receivers n remote radio heads n communications test equipment l , lt, ltc, ltm, linear technology and the linear logo are registered trademarks of linear technology corporation. all other trademarks are the property of their respective owners. if frequency response, 64k point fft, rf = 1.95ghz, lo = 1.81ghz ltm9005 ov dd 0.5v to 3.6v ognd clk gnd gain lo 3.3v saw lna dac 9005 ta01 if frequency (mhz) 80 ?80 ?30 ?40 ?50 ?60 ?70 (db) ?20 ?10 100 140120 180160 220200 9005 ta01b 0 electrical specifications subject to change
ltm9005 2 9005p p in c on f igura t ion a bsolu t e maxi m u m r a t ings supply voltage (v cc2 , v cc3 ) ..................... C0 .3v to 3.6v supply voltage (v cc1, v dd , ov dd ) ............. C0.3v to 4.0v d igital output ground voltage (ognd) ........ C 0.3v to 1v lo input power (380mhz to 4.2ghz) ................... 10 dbm lo input dc voltage ............................. C 1v to v cc1 + 1v rf input power (400mhz to 3.8ghz) ................... 12 dbm rf input dc voltage ............................................... 0 .1v en voltage ..................................... C 0.3v to v cc1 + 0.3v amp1shdn voltage ....................... C 0.3v to v cc2 + 0.3v amp2shdn voltage ....................... C 0.3v to v cc3 + 0.3v gain voltage .................................. C0.3v to v cc1 + 0.3v gain current .......................................................... 20m a digital input voltage ..................... C0.3v to (v dd + 0.3v) digital output voltage ................ C 0.3v to (ov dd + 0.3v) operating ambient temperature range ltm9005c ............................................... 0 c to 70c ltm9005i ............................................ C 40c to 85c storage temperature range .................. C 45c to 125c maximum junction temperature .......................... 1 25c caution: pins a8, a9, b8, b9, l8, l9, m8 and m9 and the rf and lo inputs are sensitive to electro-static discharge (esd). it is very important that proper esd precautions be observed when handling the ltm9005. avoid ultrasonic exposure, the ltm9005 contains a hermetic cavity filter. (notes 1, 2) lga package 204-lead (15mm 22mm 4.3mm) top view 1 2 3 4 5 6 7 8 10 9 11 12 13 14 15 16 17 lkjhgfedcb m a t jmax = 125c, ja = tdbc/w lead free finish part marking* package description temperature range ltm9005cv-aa#pbf ltm9005v aa 204-lead (15mm 22mm 4.3mm) lga 0c to 70c ltm9005iv-aa#pbf ltm9005v aa 204-lead (15mm 22mm 4.3mm) lga C40c to 85c ltm9005cv-ab#pbf ltm9005v ab 204-lead (15mm 22mm 4.3mm) lga 0c to 70c ltm9005iv-ab#pbf ltm9005v ab 204-lead (15mm 22mm 4.3mm) lga C40c to 85c consult ltc marketing for parts specified with wider operating temperature ranges. *the temperature grade is identified by a label on the shipping container. for more information on lead free part marking, go to: http://www.linear.com/leadfree/ this product is only offered in trays. for more information go to: http://www.linear.com/packaging/ o r d er i n f or m a t ion (see pin functions, pin configuration table) ltm9005 3 9005p e lec t rical c harac t eris t ics the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c. (note 3). all specifications apply at maximum gain setting. symbol parameter conditions min typ max units rf input frequency range no external matching (midband) with external matching (low band or high band) 400 1600 to 2300 3800 mhz mhz lo input frequency range no external matching with external matching 380 1000 to 4200 5000 mhz mhz rf input return loss z o = 50, 1600mhz to 2300mhz (no external matching) >12 db lo input return loss z o = 50, 1000mhz to 5000mhz (no external matching) >10 db rf input power for C1dbfs ltm9005-aa rf = 900mhz, lo = 760mhz rf = 1950mhz, lo = 1810mhz l tm9005-ab rf = 900mhz, lo = 760mhz rf = 1950mhz, lo = 1810mhz tbd tbd tbd tbd tbd C18.8 tbd C17.8 tbd tbd tbd tbd dbm dbm dbm dbm lo input power 1200mhz to 4200mhz 380mhz to 1200mhz C8 C5 C3 0 2 5 dbm dbm lo to rf leakage f lo = 380mhz to 1600mhz f lo = 1600mhz to 4000mhz ltm9005 4 9005p g ain c on t rol the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c. v cc1 = 3.3v, rf input = C1dbfs. symbol parameter conditions min typ max units gain adjustment range 20 db forward current range l 0 10 ma response time 10% to 90% gain current step tbd s input impedance xx mhz, 0.1 < i gain < 10ma 50 isolation to output rf input = tbd dbm (note 5) tbd db control voltage maximum gain gain C20db 3.3 2.55 v v dyna m ic a ccuracy the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c. (note 3). all specifications apply at maximum gain setting. c onver t er c harac t eris t ics the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c. (note 3) symbol parameter conditions min typ max units resolution (no missing codes) ltm9005-ax l 14 bits integral linearity error (note 4) if = 140mhz, ltm9005-ax tbd lsb differential linearity error if = 140mhz, ltm9005-ax tbd lsb symbol parameter conditions min typ max units snr signal-to-noise ratio at C1dbfs, within the rf passband ltm9005-aa rf = 1950mhz, lo = 1810mhz l tm9005-ab rf = 1950mhz, lo = 1810mhz tbd tbd 67.2 67 tbd tbd db db sfdr spurious free dynamic range at C1dbfs 2nd or 3rd harmonic ltm9005-aa rf = 1950mhz, lo = 1810mhz l tm9005-ab rf = 1950mhz, lo = 1810mhz tbd tbd 75 75 tbd tbd db db sfdr spurious free dynamic range at C1dbfs 4th or higher ltm9005-aa rf = 1950mhz, lo = 1810mhz l tm9005-ab rf = 1950mhz, lo = 1810mhz tbd tbd 93.5 93.5 tbd tbd db db s/(n+d) signal-to-noise plus distortion ratio at C1dbfs ltm9005-aa rf = 1950mhz, lo = 1810mhz l tm9005-ab rf = 1950mhz, lo = 1810mhz tbd tbd 60.5 62 tbd tbd db db imd3 intermodulation distortion at C7dbfs per tone ltm9005-aa rf = 1950mhz, lo = 1810mhz l tm9005-ab rf = 1950mhz, lo = 1810mhz tbd tbd 72.5 72.5 tbd tbd db db ltm9005 5 9005p digi t al i npu t s an d o u t pu t s the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c. (note 3) symbol parameter conditions min typ max units logic inputs (clk, oe, adcshdn) v ih high level input voltage v dd = 3v l 2 v v il low level input voltage v dd = 3v l 0.8 v i in input current v in = 0v to v dd l C10 10 a c in input capacitance (note 6) 3 pf amplifier shutdown (amp1shdn, amp2shdn) v ih high level input voltage v cc2 = v cc3 = 3v l 2.4 v v il low level input voltage v cc2 = v cc3 = 3v l 0.8 v i ih input high current v cc2 = v cc3 = 3v, v in = 2v 1.3 a i il input low current v cc2 = v cc3 = 3v, v in = 0.8v 0.1 a mixer enable (en) v ih high level input voltage v cc1 = 3.3v l 2.7 v v il low level input voltage v cc1 = 3.3v l 0.3 v i in input current v in = 0v to v cc1 l 53 90 a turn-on time 2.8 s turn-off time 2.9 s analog inputs (mode, sense) i mode mode input leakage l C3 3 a i sense sense input leakage 0v < sense < 1v l C3 3 a logic outputs ov dd = 3v c oz hi-z output capacitance oe = 3v (note 6) 3 pf i source output source current v out = 0v 50 ma i sink output sink current v out = 3v 50 ma v oh high level output voltage i o = C10a i o = C200a l 2.7 2.995 2.99 v v v ol low level output voltage i o = 10a i o = 1.6ma l 0.005 0.09 0.4 v v ov dd = 2.5v v oh high level output voltage i o = C200a 2.49 v v ol low level output voltage i o = 1.6ma 0.09 v ov dd = 1.8v v oh high level output voltage i o = C200a 1.79 v v ol low level output voltage i o = 1.6ma 0.09 v ltm9005 6 9005p ti m ing c harac t eris t ics the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c. (note 3) note 1: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. exposure to any absolute maximum rating condition for extended periods may affect device reliability and lifetime. note 2: all voltage values are with respect to ground with gnd and ognd wired together (unless otherwise noted). note 3: v cc1 = 3.3v, v cc2 = v cc3 = v dd = 3v, amp1shdn = amp2shdn = adcshdn = 0v, en = 3.3v, f sample = 125mhz, rf input power = C10dbm. symbol parameter conditions min typ max units f s sampling frequency l 1 125 mhz t l clk low time duty cycle stabilizer off (note 6) duty cycle stabilizer on (note 6) l l 3.8 3 4 4 500 500 ns ns t h clk high time duty cycle stabilizer off (note 6) duty cycle stabilizer on (note 6) l l 3.8 3 4 4 500 500 ns ns t ap sample-and-hold aperture delay figure 1 (note 6, note 7) 0 ns t jitter sample-and-hold acquisition delay time jitter (note 6, note 7) 0.2 ps rms t d clk to data delay c l = 5pf (note 6) l 1.4 2.7 5.4 ns data access time after oe c l = 5pf (note 6) l 4.3 10 ns bus relinquish time (note 6) l 3.3 8.5 ns pipeline latency 5 cycles note 4: integral nonlinearity is defined as the deviation of a code from a best fit straight line to the transfer curve. the deviation is measured from the center of the quantization band. note 5: noise level superimposed on the gain pin at 140mhz required to generate spur above the noise floor. note 6: guaranteed by design, not subject to test. note 7: analog input measured at l8-l9 pads. p ower r equire m en t s the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c. (note 3) symbol parameter conditions min typ max units v cc1 mixer supply range l 2.9 3.3 3.6 v v cc2 first amplifier supply range l 2.85 3.3 3.465 v v cc3 second amplifier supply range l 2.85 3.3 3.465 v v dd adc analog supply voltage l 2.85 3.3 3.465 v ov dd adc digital output supply voltage l 0.5 3.3 3.6 v i cc1 mixer supply current en = 3v l 82 92 ma i cc1(shdn) mixer shutdown supply current en = 0v l 100 a i cc2 first amplifier supply current amp1shdn = 0v l 90 105 ma i cc2(shdn) first amplifier shutdown supply current amp1shdn = 3v l 3 ma i cc3 second amplifier supply current amp2shdn = 0v l 90 105 ma i cc3(shdn) second amplifier shutdown supply current amp2shdn = 3v l 3 ma i dd adc supply current adcshdn = 0v l 132 156 ma p d(shdn) power dissipation in shutdown en = 0v, amp1shdn = amp2shdn = adcshdn = 3v, oe = 3v, no rf, no lo, no clk tbd mw p d(nap) adc nap mode power en = 0v, amp1shdn = amp2shdn = adcshdn = 3v, oe = 0v, no rf, no lo, no clk 15 mw p d(total) total power dissipation en = 3v, amp1shdn = amp2shdn = adcshdn = 0v, oe = 0v, f sample = max 1200 mw ltm9005 7 9005p ti m ing diagra m t ap n + 1 n + 2 n + 4 n + 3 n + 5 n analog input t h t d t l n ? 4 n ? 3 n ? 2 n ? 1 clk d0-d13, of 9005 td01 n ? 5 n figure 1. digital output bus timing ltm9005 8 9005p typical p er f or m ance c harac t eris t ics ltm9005-aa: 64k point 2-tone fft ltm9005: 64k point fft, maximum gain ltm9005: 64k point fft, minimum gain ltm9005: 64k point fft, minimum gain frequency (mhz) 0 amplitude (dbfs) 0 ?20 ?40 ?60 ?80 ?100 ?10 ?30 ?50 ?70 ?90 ?110 ?120 20 40 10 30 50 9005 g01 6560 15 35 5 25 45 55 f in = 1949mhz and 1951mhz ?7dbfs per tone sense = v dd frequency (mhz) 0 amplitude (dbfs) 0 ?20 ?40 ?60 ?80 ?100 ?10 ?30 ?50 ?70 ?90 ?110 ?120 20 40 10 30 50 9005 g02 6560 15 35 5 25 45 55 f in = 900mhz ?1dbfs sense = v dd frequency (mhz) 0 amplitude (dbfs) 0 ?20 ?40 ?60 ?80 ?100 ?10 ?30 ?50 ?70 ?90 ?110 ?120 20 40 10 30 50 9005 g03 6560 15 35 5 25 45 55 f in = 900mhz ?1dbfs sense = v dd ltm9005: 64k point fft, maximum gain frequency (mhz) 0 amplitude (dbfs) 0 ?20 ?40 ?60 ?80 ?100 ?10 ?30 ?50 ?70 ?90 ?110 ?120 20 40 10 30 50 9005 g04 65 60 15 35 5 25 45 55 f in = 1950mhz ?1dbfs sense = v dd frequency (mhz) 0 amplitude (dbfs) 0 ?20 ?40 ?60 ?80 ?100 ?10 ?30 ?50 ?70 ?90 ?110 ?120 20 40 10 30 50 9005 g05 65 60 15 35 5 25 45 55 f in = 1950mhz ?1dbfs sense = v dd ltm9005: lo port impedance ltm9005: lo port return loss vs frequency ltm9005: if frequency response if frequency (mhz) 40 ?? (db) 0 ?70 ?10 ?30 ?50 ?20 ?40 ?60 ?80 140 220 100 180 9005 g06 240 120 200 80 160 60 frequency (mhz) return loss (db) 9005 g08 0 ?30 ?25 ?20 ?15 ?10 ?5 100 1000 10000 no matching elements 1.81ghz match (3.3nh + 1.5pf) 840mhz match (1.5pf) ltm9005 9 9005p p in func t ions rf (pin m3): single-ended input for the rf signal. this pin is internally connected to the primary side of the rf input transformer, which has low dc resistance to ground. if the rf source is not dc blocked, then a series blocking capacitor must be used. the rf input is internally matched from 1.6ghz to 2.3ghz. operation down to 400mhz or up to 3.8ghz is possible with simple external matching. lo (pin m6): single-ended input for the local oscillator signal. this pin is internally connected to the primary side of the lo transformer, which is internally dc blocked. an external blocking capacitor is not required. the lo input is internally matched from 1ghz to 5ghz. operation down to 380mhz is possible with simple external matching. gain (pin f1): cathode of pin diode. sinking current from gain attenuates the signal. the forward voltage is approximately 1v and the output impedance is 50. en (pin h1): mixer enable pin. connecting en to v cc1 results in normal operation. connecting en to gnd disables the mixer. the en pin should not be left floating. amp1shdn (pin d4), amp2shdn (pin l16): amplifier en- able pins. connecting ampshdn to gnd results in normal operation. connecting amp1shdn to v cc2 disables the amplifier preceding the saw filter and connecting amp - 2shdn to v cc3 disables the amplifier following the saw filter. it is recommended to tie amp1shdn, amp2shdn and adcshdn together and control with 3v logic. clk (pin a11): adc clock input. the input sample starts on the positive edge. adcshdn (pin c13): adc shutdown mode selection pin. connecting adcshdn to gnd and oe to gnd results in normal operation with the adc outputs enabled. connect- ing adcshdn to gnd and oe to v dd results in normal operation with the outputs at high impedance. connecting adcshdn to v dd and oe to gnd results in nap mode with the outputs at high impedance. connecting adcshdn to v dd and oe to v dd results in sleep mode with the outputs at high impedance. oe (pin c12): output enable pin. refer to adcshdn pin function. typical p er f or m ance c harac t eris t ics ltm9005: rf port impedance ltm9005: rf port return loss vs frequency frequency (mhz) return loss (db) 9005 g10 0 ?30 ?25 ?20 ?15 ?10 ?5 100 1000 10000 no matching elements 1.95ghz match (5.6nh) 700mhz match (4.7pf) 900mhz match (2.7pf) ltm9005 10 9005p d0 C d13 (see table for pin locations): digital outputs. d13 is the msb. of (pin g15): over/under flow output. high when an over or under flow has occurred. mode (pin f15): output format and clock duty cycle stabilizer selection pin. connecting mode to gnd selects offset binary output format and turns the clock duty cycle stabilizer off. 1/3 v dd selects offset binary output format and turns the clock duty cycle stabilizer on. 2/3 v dd selects 2s complement output format and turns the clock duty cycle stabilizer on. v dd selects 2s complement output format and turns the clock duty cycle stabilizer off. sense (pin h12): reference programming pin. connect- ing sense to v dd selects the internal reference and the default input range. connecting sense to 1.5v selects the internal reference and a 3db lower input range. an external reference greater than 0.5v and less than 1v applied to sense selects the external reference. a 1v external refer - ence sets the input range equal to the default input range, a 0.5v external reference sets the input range 3db lower and an external value between 0.5v and 1v sets the input range proportionally. a8 (pin a8): test pin used during manufacturing only. connect directly to b8. keep this connection free from noise. a9 (pin a9): test pin used during manufacturing only. connect directly to b9. keep this connection free from noise. b8 (pin b8): test pin used during manufacturing only. connect directly to a8. keep this connection free from noise. b9 (pin b9): test pin used during manufacturing only. connect directly to a9. keep this connection free from noise. l8 (pin l8): test pin used during manufacturing only. connect directly to m8. keep this connection free from noise. l9 (pin l9): test pin used during manufacturing only. connect directly to m9. keep this connection free from noise. m8 (pin m8): test pin used during manufacturing only. connect directly to l8. keep this connection free from noise. m9 (pin m9): test pin used during manufacturing only. connect directly to l9. keep this connection free from noise. ognd (pins a16, a17, b17, c16 and c17): output driver ground. ov dd (pins d16 and d17): positive supply for the output drivers. this supply is internally bypassed to gnd. ov dd can be 0.5v to 3.6v. v cc1 (pins k1 and k2): 3.3v supply voltage for mixer. v cc1 is internally bypassed to gnd. v cc2 (pins b1 and c1): 3.3v supply voltage for first amplifier. v cc2 is internally bypassed to gnd. can operate at 3v if desired. v cc3 (pins m14 and m15): 3.3v supply voltage for second amplifier. v cc3 is internally bypassed to gnd. can operate at 3v if desired. v dd (pins a13 and b13): 3.3v supply voltage for adc. v dd is internally bypassed to gnd. can operate at 3v if desired. gnd (see table for pin locations): module ground. p in func t ions ltm9005 11 9005p pin configuration a b c d e f g h j k l m 1 gnd v cc2 v cc2 gnd gnd gain gnd en gnd v cc1 gnd gnd 2 gnd gnd gnd gnd gnd gnd gnd gnd gnd v cc1 gnd gnd 3 gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd rf 4 gnd gnd gnd amp1 shdn gnd gnd gnd gnd gnd gnd gnd gnd 5 gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd 6 gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd lo 7 gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd 8 a8 b8 gnd gnd gnd gnd gnd gnd gnd gnd l8 m8 9 a9 b9 gnd gnd gnd gnd gnd gnd gnd gnd l9 m9 10 gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd 11 clk gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd gnd 12 gnd gnd oe gnd gnd gnd gnd sense gnd gnd gnd gnd 13 v dd v dd adc shdn gnd gnd gnd gnd gnd gnd gnd gnd gnd 14 d0 d2 gnd gnd gnd gnd gnd gnd gnd gnd gnd v cc3 15 d1 d3 gnd gnd d5 mode of gnd gnd gnd gnd v cc3 16 ognd d4 ognd ov dd d6 d9 d11 d13 gnd gnd amp2 shdn gnd 17 ognd ognd ognd ov dd d7 d8 d10 d12 gnd gnd gnd gnd top view of lga package (looking through component) b lock diagra m simplified block diagram v cc2 v dd ov dd d13 ? d0 of clk mode sense lo v cc1 saw 9005 bd01 50 gain amp1 shdn 1st amplifier v cc3 bpf oe 2nd amplifier 14-bit adc output drivers 1.5v reference range select 50 0.1f adc shdn reference buffer amp2 shdn ognd en rf p in func t ions ltm9005 12 9005p o pera t ion d escription the ltm9005 is an integrated system in a package (sip) that includes a high-speed 14-bit a/d converter, two low- distortion fixed-gain amplifiers, a saw filter, a continuously variable attenuator and an active mixer. the ltm9005 is designed for very compact if sampling applications with rf input frequencies up to 3.8ghz. typical applications include wireless base stations, remote radio heads and communications test instrumentation. all of the supply bypassing and passive filtering has been included inside the ltm9005 making the total solution size extremely small. furthermore, the tight coupling makes the performance more consistent and less dependent on board layout. great care has been taken to protect sensi- tive signals from noise within the module package and isolate the rf section from the digital section. the overall gain is optimized for the dynamic range of the adc relative to the rf input level allowed by the mixer. the equivalent cascaded noise figure is 16db. the rf input level for C1dbfs is typically C19dbm. the following sections describe the operation of each functional element. the sip technology allows the ltm9005 to be customized and this is described in the semi-custom options section. the outline of the remaining sections follows the basic functional elements as shown in figure 2. ? rf input port ? lo input port ? adc clock input port ? gain control input ? sense and reference input ? digital outputs ? shutdown control ? power supplies ? layout s emi -c ustom o p tions the module construction affords a new level of flexibility in application-specific standard products. standard mixed- signal, if and rf components can be integrated regardless of their process technology and matched with passive components to a particular application. the ltm9005 - aa, as the first example, is configured with a 14-bit adc sampling at rates up to 125msps. the total system gain is 22db of which 20db is variable. the if is fixed by the sa w filter at 140mhz with 16mhz bandwidth. the rf range is matched for 1.6ghz to 2.3ghz with external matching required to achieve 400mhz to 3.8ghz. however, other options are possible through linear technologys semi-custom development program. linear technology has in place a program to deliver other speed, resolution, rf/if range, gain and filter configurations for nearly any specified application. adc resolution and speed options range from 14-bits and 125msps to 10-bits and 10msps. the if can be set from 70mhz to about 270mhz with bandwidths from a few mhz to about 60mhz. these semi-custom designs are based on existing adcs, am- plifiers, filters and mixers with appropriately modified matching networks. the final subsystem is then tested to the exact parameters defined for the application. the final result is a fully integrated, accurately tested and optimized solution in the same package. for more details on the semi-custom receiver subsystem program, contact linear technology. figure 2. basic functional elements ltm9005 v cc2 v dd ov dd ognd adc clk adc gain control gnd lo mixer attenuator rf v cc1 v cc3 saw bpf 1st amplifier 2nd amplifier 9005 f02 the applications section describes the design consider - ations and recommendations for interfacing to the key ports and functions as well as board layout in the follow- ing order: ltm9005 13 9005p o pera t ion down-converting mixer the mixer stage consists of a high linearity double-bal- anced mixer, rf buffer amplifier, high speed limiting lo buffer amplifier and bias/enable circuits. the rf and lo inputs are both single ended. low side or high side lo injection can be used. the rf input consists of an integrated transformer and a high linearity differential amplifier. the primary terminals of the transformer are connected to the rf input and ground. the secondary side of the transformer is internally con - nected to the amplifiers differential inputs. the lo input consists of an integrated transformer and high speed limiting differential amplifiers. the amplifiers are designed to precisely drive the mixer for the highest linearity and the lowest noise figure. attenuator a dual pin diode with common-cathode connection is used for continuously variable attenuation. the anodes are connected to the outputs of the mixer and pulled up to v cc1 through 100nh inductors. the cathode includes a series 50 resistor to gain. see the gain control input section for applications information. first and second amplifiers the amplifiers used in the ltm9005 are low noise and low distortion fully differential adc drivers. the ampli- fiers are fully differential amplifiers with on chip feedback resistors. saw filter a high selectivity, surface acoustic wave (saw) filter is integrated in the ltm9005. (applications to provide additional text) band-pass filter an l-c bandpass filter follows the second amplifier to prevent aliasing and to minimize the noise contribution of the second amplifier. (applications to provide additional text) analog to digital converter the analog-to-digital converter (adc) is a cmos pipelined multistep converter. the converter has six pipelined adc stages; a sampled analog input will result in a digitized value five cycles later (see digital output bus timing). the clk input is single-ended. the adc has two phases of operation, determined by the state of the clk input pin. each pipelined stage contains an adc, a reconstruction dac and an interstage residue amplifier. in operation, the adc quantizes the input to the stage and the quantized value is subtracted from the input by the dac to produce a residue. the residue is amplified and output by the residue amplifier. successive stages operate out of phase so that when the odd stages are outputting their residue, the even stages are acquiring that residue and visa versa. when clk is low, the analog input is sampled differen- tially directly onto the input sample-and-hold capacitors. at the instant that clk transitions from low to high, the sampled input is held. while clk is high, the held input voltage is buffered by the s/h amplifier which drives the first pipelined adc stage. the first stage acquires the output of the s/h during this high phase of clk. when clk goes back low, the first stage produces its residue which is acquired by the second stage. at the same time, the input s/h goes back to acquiring the analog input. when clk goes back high, the second stage produces its residue which is acquired by the third stage. an identical process is repeated for the third, fourth and fifth stages, resulting in a fifth stage residue that is sent to the sixth stage adc for final evaluation. each adc stage following the first has additional range to accommodate flash and amplifier offset errors. results from all of the adc stages are digitally synchronized such that the results can be properly combined in the correction logic before being sent to the output buffer. ltm9005 14 9005p a pplica t ions i n f or m a t ion rf input port the rf input is shown in figure 3 and is internally matched from 1.6ghz to 2.3ghz, requiring no external components over this frequency range. the input return loss, shown in figure 4, is typically 12db at the band edges. the input match at the lower band edge can be optimized with a series 3.9pf capacitor at pin m3, which improves the 1.6ghz return loss to greater than 25db. likewise, the 2.3ghz match can be improved to greater than 25db with a series 1.5nh inductor. a series 2.7nh/2.2pf network will simultaneously optimize the lower and upper band edges and expand the rf input bandwidth to 1.2ghz to 2.5ghz. measured rf input return losses for these three cases are also plotted in figure 4. figure 3. rf input schematic figure 5. rf input return loss with and without matching alternatively, the input match can be shifted as low as 400mhz or up to 3800mhz by adding a shunt capacitor (c5) to the rf input. a 450mhz input match is realizedwith c5 = 12pf, located 6.5mm away from pin m3 on a 50 input transmission line. a 900mhz input match requires c5 = 3.9pf, located at 1.7mm. a 3.6ghz input match is realized with c5 = 1pf, located at 2.9mm. this series transmission line/shunt capacitor matching topology allows the ltm9005 to be used for multiple frequency standards without circuit board layout modifications. the series transmission line can also be replaced with a series chip inductor for a more compact layout. input return losses for the 450mhz, 900mhz, 2.6ghz and 3.6ghz applications are plotted in figure 5. the input return loss with no external matching is repeated in figure 5 for comparison. the 2.6ghz rf input match uses the high-pass matching network shown in figure 3 with c5 = 3.9pf and l5 = 3.6nh. the high-pass input matching network is also used to create a wideband or dual-band input match. for example, with c5 = 3.3pf and l5 = 10nh, the rf input is matched from 800mhz to 2.2ghz, with optimum matching in the 800mhz to 1.1ghz and 1.6ghz to 2.2ghz bands, simultaneously. figure 4. series reactance matching rf in z o = 50 l = l (mm) c5 rf 9005 f03 rf in c5 l5 low-pass match for 450mhz, 900mhz and 3.6ghz rf high-pass match for 2.6ghz rf and wideband rf to mixer 3 frequency (ghz) 0.2 ?30 rf port return loss (db) ?25 ?20 ?15 ?10 1.2 2.2 3.2 4.2 9005 f04 ?5 0 0.7 1.7 2.7 3.7 series 2.7nh and 2.2pf no ext match series 1.5nh series 3.9pf frequency (ghz) 0.2 ?30 rf port return loss (db) ?25 ?20 ?15 ?10 1.2 2.2 3.2 4.2 9005 f05 ?5 0 0.7 1.7 2.7 3.7 450mhz l = 6.5mm c5 = 12pf 2.6ghz series 3.9pf shunt 3.6nh 3.6ghz l = 2.9mm c5 = 1pf 900mhz l = 1.7mm c5 = 3.9pf no ext match ltm9005 15 9005p a pplica t ions i n f or m a t ion rf input impedance and s11 versus frequency (with no external matching) are listed in table 1 and referenced to pin m3. the s11 data can be used with a microwave circuit simulator to design custom matching networks and simulate board-level interfacing to the rf input filter. table 1 rf input impedance vs frequency frequency (mhz) input impedance s11 mag angle 50 4.6 + j2.3 0.832 174.7 300 9.1 + j11.2 0.706 153.8 450 12.0 + j14.5 0.639 145.8 600 14.7 + j17.4 0.588 138.7 900 20.5 + j23.3 0.506 123.4 1300 34.4 + j30.3 0.380 97.5 1700 59.6 + j23.8 0.299 55.8 1950 69.2 + j2.8 0.163 6.9 2200 59.2 C j18.1 0.184 C53.5 2450 41.5 C j24.5 0.274 C94.2 2700 28.3 C j21.3 0.374 C120.3 3000 19.0 C j13.5 0.481 C145.5 3300 13.9 C j5.1 0.568 C167.3 3600 10.8 + j3.4 0.645 171.9 3900 9.4 + j12.3 0.700 151.4 rf input overload in the event of an overload condition at the rf in- put, (applications to provide additional text following characterization). lo input port the lo input, shown in figure 6, is internally matched from 1ghz to 5ghz. the input match can be shifted down, as low as 750mhz, with a single shunt capacitor (c4) on pin m6. one example is plotted in figure 7 where c4 = 2.7pf produces a 50mhz to 1ghz match. figure 6. lo input schematic figure 7. lo input return loss lo input matching below 750mhz requires the series inductor (l4)/shunt capacitor (c4) network shown in figure 6. two examples are plotted in figure 7 where l4 = 2.7nh/c4 = 3.9pf produces a 650mhz to 830mhz match and l4 = 10nh/c4 = 8.2pf produces a 460mhz to 560mhz match. the optimum lo drive is C3dbm for lo frequencies above 1.2ghz, although the amplifiers are designed to accom- modate several db of lo input power variation without significant mixer performance variation. below 1.2ghz, 0dbm lo drive is recommended for optimum noise figure, although C3dbm will still deliver good conversion gain and linearity. lo in c4 l4 lo v cc1 limiter v ref 9005 f06 external matching for lo < 1ghz to mixer 15 regulator lo frequency (ghz) 0.3 l4 = 10nh c4 = 8.2pf l4 = 2.7nh c4 = 3.9pf l4 = 0 c4 = 2.7pf ?30 lo port return loss (db) ?10 0 1 5 9005 f07 ?20 no ext match ltm9005 16 9005p a pplica t ions i n f or m a t ion custom matching networks can be designed using the port impedance data listed in table 2. this data is referenced to the lo pin with no external matching. table 2 lo input impedance vs frequency frequency (mhz) input impedance s11 mag angle 50 10.0 C j326 0.991 C17.4 300 80.5 C j41.9 0.820 C99.2 500 11.8 C j10.1 0.632 C155.9 700 18.8 + j10.9 0.474 151.8 900 35.0 + j27.4 0.350 100.8 1200 72.9 + j19.3 0.241 31.3 1500 70.0 C j12.6 0.196 C26.1 1800 55.0 C j17.0 0.167 C64.3 2200 47.8 C j9.7 0.102 C97.2 2600 53.6 C j1.9 0.039 C26.8 3000 66.7 + j0.7 0.143 2.1 3500 82.1 C j13.9 0.263 C17.4 4000 69.0 C j30.1 0.290 C43.5 4500 43.7 C j13.2 0.154 C107.5 5000 36.4 + j19.8 0.271 111.6 lo input overload text to come. reference operation the ltm9005 includes an internal voltage reference that is internally bypassed. an external reference can be used or the internal reference can be configured for two pin selectable input ranges. tying the sense pin to v dd selects the default range; tying the sense pin to 1.5v selects a 3db lower range. other voltage ranges in-between the pin selectable ranges can be programmed. an external reference can be used by applying its output directly or through a resistive divider figure 8. sinusoidal single-ended clk driver to sense. it is not recommended to drive the sense pin with a logic device. the sense pin should be tied to the appropriate level as close to the converter as possible. if the sense pin is driven externally, note that this pin is filtered internally with a 50 series resistor and a 0.1f capacitor to ground. adc clock input the clk input can be driven directly with a cmos or ttl level signal. a sinusoidal clock can also be used along with a low-jitter squaring circuit before the clk pin (figure 8). clk 50 0.1f 0.1f 4.7f 1k 1k ferrite bead clean supply sinusoidal clock input 9005 f08 nc7svu04 ltm9005 the noise performance of the adc can depend on the clock signal quality as much as on the analog input. any noise present on the clk signal will result in additional aperture jitter that will be rms summed with the inherent adc aperture jitter. in applications where jitter is critical, use as large an amplitude as possible. also, if the adc is clocked with a sinusoidal signal, filter the clk signal to reduce wideband noise and distortion products generated by the source. figure 9 and figure 10 show alternatives for converting a differential clock to the single-ended clk input. the use of a transformer provides no incremental contribution ltm9005 17 9005p a pplica t ions i n f or m a t ion to phase noise. the lvds or pecl to cmos translators provide little degradation below 70mhz, but at 140mhz will degrade the snr compared to the transformer solution. the nature of the received signals also has a large bearing on how much snr degradation will be experienced. for high crest factor signals such as wcdma or ofdm, the use of these translators will have a lesser impact. the transformer in the example may be terminated with the appropriate termination for the signaling in use. the use of a transformer with a 1:4 impedance ratio may be desirable in cases where lower voltage differential signals are considered. the center tap may be bypassed to ground through a capacitor close to the adc if the differential signals originate on a different plane. the use of a capacitor at the input may result in peaking, and depending on transmission line length may require a 10 to 20 series resistor to act as both a lowpass filter for high frequency noise that may be induced into the clock line by neighboring digital signals, as well as a damping mechanism for reflections. maximum and minimum conversion rates the maximum conversion rate for the adc is 125msps. the lower limit of the sample rate is determined by the droop of the sample-and-hold circuits. the pipelined ar - chitecture of this adc relies on storing analog signals on small valued capacitors. junction leakage will discharge the capacitors. the specified minimum operating frequency for the ltm9005 is 1msps. clock duty cycle stabilizer an optional clock duty cycle stabilizer circuit ensures high performance even if the input clock has a non 50% duty cycle. using the clock duty cycle stabilizer is recommended for most applications. to use the clock duty cycle stabilizer, the mode pin should be connected to 1/3v dd or 2/3v dd using external resistors. this circuit uses the rising edge of the clk pin to sample the analog input. the falling edge of clk is ignored and the internal falling edge is generated by a phase-locked loop. the input clock duty cycle can vary from 40% to 60% and the clock duty cycle stabilizer will maintain a constant 50% internal duty cycle. if the clock is turned off for a long period of time, the duty cycle stabilizer circuit will require a hundred clock cycles for the pll to lock onto the input clock. for applications where the sample rate needs to be changed quickly, the clock duty cycle stabilizer can be disabled. if the duty cycle stabilizer is disabled, care should be taken to make the sampling clock have a 50% (5%) duty cycle. gain control input the total receiver gain is continuously adjustable using a pin diode. maximum gain is set by forcing gain to v cc1 . figure 9. clk driver using an lvds or pecl to cmos converter figure 10. lvds or pecl clk drive using a transformer clk 100 0.1f 4.7f ferrite bead clean supply if lvds use fin1002 or fin1018. for pecl, use az1000elt21 or similar 9005 f09 ltm9005 clk 5pf-30pf etc1-1t 0.1f v cm ferrite bead differential clock input 9005 f10 ltm9005 ltm9005 18 9005p the dac used to control gain will contribute a non-neg- ligible amount of voltage noise. (text to comediscuss further and provide noise analysis.) in some applications it may be sufficient to permanently set the gain to a fixed level. this simplifies the circuitry as a fixed resistor to ground can be implemented. d igit al o utputs table 3 shows the relationship between the analog input voltage, the digital data bits, and the over flow bit. table 3. output codes vs input voltage, ltm9005-aa input (sense = v dd ) of d13 C d0 (offset binary) d13 C d0 (2s complement) overvoltage maximum 1 0 0 11 1111 1111 1111 11 1111 1111 1111 11 1111 1111 1110 01 1111 1111 1111 01 1111 1111 1111 01 1111 1111 1110 0 0 0 0 10 0000 0000 0001 10 0000 0000 0000 01 1111 1111 1111 01 1111 1111 1110 00 0000 0000 0001 00 0000 0000 0000 11 1111 1111 1111 11 1111 1111 1110 minimum undervoltage 0 0 1 00 0000 0000 0001 00 0000 0000 0000 00 0000 0000 0000 10 0000 0000 0001 10 0000 0000 0000 10 0000 0000 0000 a pplica t ions i n f or m a t ion figure 11. automatic gain control circuit minimum gain is achieved by sinking approximately 10ma from the gain pin. if the gain is to be adjusted as part of an active control loop then the circuit in figure 11 can be used. see the typical performance characteristics for the transfer function. figure 12. digital output buffer digital output modes figure 12 shows an equivalent circuit for a single output buffer. each buffer is powered by ov dd and ognd, isolated from the adc power and ground. the additional n-channel transistor in the output driver allows operation down to low voltages. the internal resistor in series with the output makes the output appear as 50 to external circuitry and may eliminate the need for external damping resistors. as with all high speed/high resolution converters the digital output loading can affect the performance. the digital outputs of the adc should drive a minimal capacitive load to avoid possible interaction between the digital outputs and sensitive input circuitry. for full speed operation, the capacitive load should be kept under 10pf. lower ov dd voltages will also help reduce interference from the digital outputs. data format using the mode pin, the adc parallel digital output can be selected for offset binary or 2s complement format. connecting mode to gnd or 1/3v dd selects straight binary output format. connecting mode to 2/3v dd or v dd selects 2s complement output format. an external resistive divider can be used to set the 1/3v dd or 2/3v dd logic values. table 5 shows the logic states for the mode pin. ltm9005 9005 f12 ov dd v dd v dd 43 typical data output ognd ov dd 0.5v to 3.6v predriver logic data from latch oe 49.9 tbd 9005 f11 ltm9005 gain v cc1 ltm9005 19 9005p a pplica t ions i n f or m a t ion table 4. mode pin function mode pin output format clock duty cycle stabilizer 0 straight binary off 1/3v dd straight binary on 2/3v dd 2s complement on v dd 2s complement off overflow bit when of outputs a logic high the converter is either over - ranged or underranged. output clock the adc has a delayed version of the clk input available as a digital output, clkout. the falling edge of the clkout pin can be used to latch the digital output data. output driver power separate output power and ground pins allow the output drivers to be isolated from the analog circuitry. the power supply for the digital output buffers, ov dd , should be tied to the same supply that powers the logic being driven. for example, if the converter drives a dsp powered by a 1.8v supply, then ov dd should be tied to that same 1.8v supply. ov dd can be powered with any voltage from 500mv up to the v dd of the part. ognd can be powered with any voltage from gnd up to 1v and must be less than ov dd . the logic outputs will swing between ognd and ov dd . output enable the outputs may be disabled with the output enable pin, oe. oe high disables all data outputs including of. the data access and bus relinquish times are too slow to allow the outputs to be enabled and disabled during full speed operation. the output hi-z state is intended for use during long periods of inactivity. shutdown modes the ltm9005 provides several levels of shutdown. the mixer, both amplifiers and the adc can all be shut down independently. furthermore, the adc may be placed in shutdown or nap modes to conserve power. connecting adcshdn to gnd results in normal operation. connecting adcshdn to v dd and oe to v dd results in sleep mode, which powers down all circuitry including the reference and the adc typically dissipates 1mw. when exiting sleep mode, it will take milliseconds for the output data to become valid because the reference capacitors have to recharge and stabilize. connecting adcshdn to v dd and oe to gnd results in nap mode and the adc typically dis- sipates 30mw. in nap mode, the on-chip reference circuit is kept on, so that recovery from nap mode is faster than that from sleep mode, typically taking 100 clock cycles. in both sleep and nap modes, all digital outputs are disabled and enter the hi-z state. amplifier shutdown when the adc is in sleep or nap mode, it is recommended to shut down both the first and second amplifiers using their respective shutdown pins, amp1shdn and amp- 2shdn. connecting ampshdn to gnd results in normal operation. connecting amp1shdn to v cc2 disables the amplifier preceding the saw filter and connecting amp - 2shdn to v cc3 disables the amplifier following the saw filter. it is recommended to tie amp1shdn, amp2shdn and adcshdn together and control with 3v logic. mixer enable interface the mixer is enabled and shut down differently than the other functions in the ltm9005. the voltage necessary to turn on the mixer is 2.7v. to disable the mixer, the enable voltage must be less than 0.3v. if the en pin is allowed to float, the mixer will tend to remain in its last operating state. thus it is not recommended that the enable function be used in this manner. if the shutdown function is not required, then the en pin should be connected directly to v cc1 . supply sequencing the v cc pins provide the supplies to the mixer and both amplifiers. the v dd pin provides the supply to the adc. each v cc pin is brought out separately and internally bypassed. the mixer, both amplifiers and the adc are separate integrated circuits within the ltm9005; however, there are no supply sequencing considerations beyond ltm9005 20 9005p standard practice. it is recommended that all supply inputs use the same low noise, 3.3v supply, but the adc and the amplifiers may be operated from a lower voltage level if desired. all three rails can operate from the same 3.3v linear regulator but place a ferrite bead between the supply pins. separate linear regulators can be used without additional supply sequencing circuitry if they have common input supplies. grounding and bypassing the ltm9005 requires a printed circuit board with a clean unbroken ground plane; a multilayer board with an internal ground plane is recommended. the pinout of the ltm9005 has been optimized for a flow-through layout so that the interaction between inputs and digital outputs is minimized. the placement of critical pads allows for those signals to be routed on the top layer. the ground planes within the ltm9005 are broken in to three areas: rf ground, if ground and digital ground. the mixer (v cc1 ) and first amplifier (v cc2 ) return to rf ground. in figure ?, this area is to the left of the line start- ing between pads m6 and m7 and ending between pads a10 and a11. the rf ground plane is bridged to the if ground plane by the saw filter. all gnd pins can connect to the same ground plane. it is not necessary to break these ground planes on the circuit board but the pads are separated and available for use. the second amplifier (v cc3 ) and the analog portion of the adc (v dd ) return to if ground. all gnd pads to the right of line described above are if ground. the if ground plane is bridged to the digital ground plane by the adc die. the digital ground plane uses the ognd pads and extends under all of the digital output pads. the ltm9005 is internally bypassed with the mixer (v cc1 ), first amplifier (v cc2 ), second amplifier (v cc3 ) and adc (v dd ) supplies returning to ground (gnd). the digital output supply (ov dd ) is returned to ognd. additional bypass capacitance is optional and may be required if power supply noise is significant. heat transfer most of the heat generated by the ltm9005 is transferred through the bottom-side ground pads. for good electrical and thermal performance, it is critical that all ground pins are connected to a ground plane of sufficient area with as many vias as possible. a pplica t ions i n f or m a t ion if gnd digital gnd 9005 f13 a1 rf gnd figure 13 ltm9005 21 9005p a pplica t ions i n f or m a t ion recommended layout the high integration of the ltm9005 makes the pcb board layout very simple and easy. however, to optimize its electri - cal and thermal performance, some layout considerations are still necessary. ? use large pcb copper areas for ground. this helps to dissipate heat in the package through the board and also helps to shield sensitive on-board analog signals. common ground (gnd) and output ground (ognd) are electrically isolated on the ltm9005, but can be connected on the pcb underneath the part to provide a common return path. ? use multiple ground vias. using as many vias as possible helps to improve the thermal performance of the board and creates necessary barriers sepa-rating analog and digital traces on the board at high frequencies. ? separate analog and digital traces as much as pos- sible, using vias to create high-frequency barriers. this will reduce digital feedback that can reduce the signal-to-noise ratio (snr) and dynamic range of the ltm9005. ? connect pad a8 to b8 on the top layer with no other connections. these pads should not be connected to any other circuitr y or ground. keep these two pads free from noise. connect a9 to b9, l8 to m8 and l9 to m9 in the same manner. figure # through ## give a good example of the recom- mended layout. the quality of the paste print is an important factor in producing high yield assemblies. it is recommended to use a type 3 or 4 printing no-clean solder paste. the solder stencil design should follow the guidelines outlined in ap- plication note 100. avoid ultrasonic cleaning. the ltm9005 employs gold-finished pads for use with pb-based or tin-based solder paste. it is inherently pb-free and complies with the jedec (e4) standard. the materi - als declaration is available online at http://www.linear. com/leadfree/mat_dec.jsp. ltm9005 22 9005p dc1391b.zip layer: inner4.lyr 26 jan 2009,08:23 am dc1391b.zip layer: bottom.sol 26 jan 2009,08:23 am a pplica t ions i n f or m a t ion dc1391b.zip layer: top.cmp 26 jan 2009,08:23 am layer 1 layer 2 dc1391b.zip layer: inner1.lyr 26 jan 2009,08:23 am layer 3 layer 4 ltm9005 23 9005p information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no representa - tion that the interconnection of its circuits as described herein will not infringe on existing patent rights. p ackage descrip t ion 1 2 3 4 5 6 7 8 10 9 11 12 13 14 15 16 17 l k j h g f e d c b m a notes: 1. dimensioning and tolerancing per asme y14.5m-1994 2. all dimensions are in millimeters land designation per jesd mo-222 5. primary datum -z- is seating plane 6. the total number of pads: 204 4 3 details of pad #1 identifier are optional, but must be located within the zone indicated. the pad #1 identifier may be either a mold or marked feature symbol aaa bbb eee tolerance 0.15 0.10 0.05 4.22 ? 4.42 detail b detail b substrate mold cap 0.27 ? 0.37 3.95 ? 4.05 bbb z z 22 bsc package top view 15 bsc 4 pad 1 corner x y aaa z aaa z 20.32 bsc 1.27 bsc 0.12 ? 0.28 package bottom view 3 pads see notes suggested pcb layout top view 0.0000 1.2700 1.2700 2.5400 2.5400 3.8100 3.8100 5.0800 5.0800 6.3500 6.3500 7.6200 8.8900 10.1600 6.9850 6.9850 5.7150 5.7150 4.4450 4.4450 3.1750 3.1750 1.9050 1.9050 0.6350 0.6350 0.0000 7.6200 8.8900 10.1600 lga 204 0209 rev ? ltmxxxxxx module tray pin 1 bevel package in tray loading orientation component pin ?a1? ?(0.635) pad 1 detail a 13.97 bsc detail a 0.635 0.025 sq. 204x s yxeee lga package 204-lead (22mm 15mm 4.32mm) (reference ltc dwg # 05-08-1841 rev ?) ltm9005 24 9005p linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 fax : (408) 434-0507 www.linear.com linear technology corporation 2010 lt 1010 ? printed in usa r ela t e d p ar t s part number description comments ltc2225 12-bit, 10msps adc 60mw, 71db snr, 5mm w 5mm qfn ltc2226 12-bit, 25msps adc 75mw, 71db snr, 5mm w 5mm qfn ltc2227 12-bit, 40msps adc 125mw, 71db snr, 5mm w 5mm qfn ltc2228 12-bit, 65msps adc 210mw, 71db snr, 5mm w 5mm qfn ltc2229 12-bit, 80msps adc 230mw, 70.6db snr, 5mm w 5mm qfn ltc2245 14-bit, 10msps adc 60mw, 74.4db snr, 5mm w 5mm qfn ltc2246 14-bit, 25msps adc 75mw, 74db snr, 5mm w 5mm qfn ltc2247 14-bit, 40msps adc 125mw, 74db snr, 5mm w 5mm qfn ltc2248 14-bit, 65msps adc 210mw, 74db snr, 5mm w 5mm qfn ltc2249 14-bit, 80msps adc 230mw, 73db snr, 5mm w 5mm qfn ltc2252 12-bit, 105msps, 3v adc, lowest power 320mw, 70.2db snr, 32-pin qfn package ltc2253 12-bit, 125msps adc, 3v adc, lowest power 395mw, 70.2db snr, 32-pin qfn package ltc2254 14-bit, 105msps, 3v adc, lowest power 320mw, 72.4db snr, 88db sfdr, 32-pin qfn package ltc2255 14-bit, 125msps adc, 3v adc, lowest power 395mw, 72.5db snr, 88db sfdr, 32-pin qfn package lt5527 400mhz to 3.7ghz, 5v high signal level downconverting mixer 23.5dbm iip3 at 1.9ghz, nf = 12.5db, single-ended rf and lo ports lt5557 800mhz to 2.7ghz high linearity direct conversion quadrature demodulator 24.7dbm iip3 at 1.9ghz, nf = 11.7db, single-ended rf and lo ports, 3.3v supply ltc6400-8/ltc6400-14/ ltc6400-20/ltc6400-26 low noise, low distortion differential amplifier for 300mhz if, fixed gain of 8db, 14db, 20db or 26db 3v, 90ma, 39.5dbm oip3 at 300mhz, 6db nf ltc6401-8/ltc6401-14/ ltc6401-20/ltc6401-26 low noise, low distortion differential amplifier for 140mhz if, fixed gain of 8db, 14db, 20db or 26db 3v, 45ma, 45.5dbm oip3 at 140mhz, 6db nf ltm9001 16-bit, high-speed receiver subsystem module receiver with adc, fixed gain amplifier and anti-alias filter in 11.25mm w 11.25mm lga ltm9002 14-bit, high-speed dual receiver subsystem module receiver with dual adc, dual amplifiers, anti-alias filters and a dual trim dac in 15mm w 11.25mm lga |
Price & Availability of LTM9005IV-ABPBF
 |
|
|
|
|
All Rights Reserved © IC-ON-LINE 2003 - 2022 |
| [Add Bookmark] [Contact Us] [Link exchange] [Privacy policy] |
|
Mirror Sites : [www.datasheet.hk]
[www.maxim4u.com] [www.ic-on-line.cn]
[www.ic-on-line.com] [www.ic-on-line.net]
[www.alldatasheet.com.cn]
[www.gdcy.com]
[www.gdcy.net] |